Multi level cells (MLC) flash memory cells may store multiple bits per cell. These multiple bits per cell may include a least significant bit (LSB), a most significant bit (MSB) and zero or more central significant bits (CSBs).
Bits of different order (also referred to as bits of different significance) are stored by programmings of different significance. MSB bits are programmed by MSB programming, LSB bits are programmed by LSB programming and each CSB bit is programmed by the appropriate CSB programming. Higher significance bit programming is faster than lower significance bit programming.
When performing MSB programming a host interface of a memory controller can slow down the programming process (form a bottleneck) while when performing LSB programming (which is slower than MSB programming) the flash memory module can slow down the programming process (form a bottleneck).
FIG. 1 is a prior art timing diagram 100 that shows (a) data being written 10 by a host computer to a host interface of a memory controller, (b) data being written to a flash memory module from a flash memory module interface of a memory controller, (c) a first idle event 31 in which a flash memory module waits for data from a host computer and (d) a second idle event 32 in which the host computer is barred from sending more information—as the programming of data to a flash memory module did not end.
There is a growing need to increase the programming speed especially in devices where an internal volatile memory of a memory controller is not big enough to smooth (by buffering) the incoming data.